1. Field of the Invention
This invention relates generally to a method for fabricating semiconductor devices. More specifically it relates to processes for forming BiCMOS devices.
2. Description of Related Art
Semiconductor integrated circuits that have both bipolar and CMOS device structures are known as BiCMOS circuits. These BiCMOS circuits can often combine the advantages of the high speed bipolar device structures with the high power performance of CMOS device structures to result in a solution neither technology could offer alone.
However, when fabricating such a BiCMOS integrated circuit, it is often found necessary to insert bipolar processing steps at various points into the CMOS process flow to realize the desired device characteristics. Thus, a typical BiCMOS integrated circuit process will have more process steps than either a bipolar or CMOS process taken singly. For example, Embabi et al. in "Digital BiCMOS Integrated Circuit Design", Kluwer Academic Publishers p. 32-38 (1993), summarize BiCMOS processes as falling into one of three categories, Low Cost; Medium Performance; and High Performance. Low Cost processes are described as requiring only one additional masking step and produce bipolar devices with low cut-off frequencies (f.sub.T) and poor current drive. Medium Performance processes are described as requiring only three additional masking steps and produce devices having f.sub.T approaching 5 gigahertz (GHz) with better current drive. Finally, High Performance processes are described as requiring at least four additional masking steps and produce devices having f.sub.T in excess of 5 GHz.
These additional process steps, required to integrate bipolar devices into a CMOS process, undesirably increase the complexity and cost of the fabrication process. In some cases, this increase in complexity and cost outweighs the advantages in circuit performance realized by the BiCMOS structure. For example a process yielding bipolar NPN transistors with a cut-off frequency in excess of 10 gigahertz (GHz), could require more than four additional masking and doping steps rendering its use commercially infeasible, whereas a circuit produced without additional steps would be a commercial success.
Furthermore, the typical high performance BiCMOS process requires the formation of an epitaxial layer which may be problematic. Modern fabrication techniques allow the thickness of the epitaxial layer to be controlled only to within approximately 0.05 to 0.1 .mu.m. Thus, where it is desired to form an epitaxial layer of 0.5 .mu.m, a processing error of approximately 10 to 20% is introduced. Additionally, the surface cleaning required before epitaxial growth, and the annealing of the buried layer, not only increases costs but also consumes valuable time.
Therefore, it would be desirable to form high performance BiCMOS structures without requiring any additional masking and/or doping steps beyond those typically used in forming CMOS devices. In addition, it would be desirable to form high performance BiCMOS structures without requiring formation of an epitaxial silicon layer. In this manner, process complexity is minimized and cost reduced.